The newest processor subsystems for computing devices run on very high speed interconnects and include increasingly higher frequency processors. In order to take full advantage of the extra processor computing power such advanced processor subsystems provide, the amounts of system resources, such as main memory, must be increased. Traditionally, each additional memory subsystem added to a computing system has had its own memory controller connected directly to the processor/system bus. Dedicated memory controllers for each subsystem were necessary because of the limitations on the number of row address strobe/column address strobe (RAS/CAS) lines that each individual memory controller could drive. By attaching each memory subsystem to the processor/system bus directly, all memory subsystems thus have the same performance criteria, in terms of, e.g., latency, timing, bandwidth, etc.
With the ever-increasing bus frequencies available, however, loads on the processor/system bus must be minimized so as not to degrade system performance. Direct coupling of multiple memory controllers and associated memory subsystems to the processor/system bus, therefore, should be avoided, if possible. Thus, it is desired to provide a capability for expansion of the memory resources in a computing system, without a concomitant increase in load on the processor/system bus and without a reduction in memory transaction performance.